In reply to dave_59:
Yeah, our code is littered with code like:
`define NON_NEG_MSB( a ) ( ( a ) ? ( ( a ) - 1 ) : ( 0 ) )
parameter FOO = 8;
input wire [ `NON_NEG_MSB( FOO ) : 0 ] bar_i
Here, a value of FOO = 0 is a legal degenerate case. But there’s no way to declare a zero-width port. I’d love a better solution rather than this macro trick to represent “0” of something in verilog, but don’t have any real suggestions.
In my mind the degenerate case for a variable-width signal of zero length is an event. However that doesn’t really help much with respect to how one could implement it in the current verilog grammar.
No language is perfect…
Regards,
Mark