System Verilog Assertions: Difference between ##1 and |=>

SystemVerilog
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1

Hi,

I am not able to exactly identify the difference between (##0 and |->) or (##1 and |=>). Can they be used interchangeably? Or is there a subtle difference between the two?

Please let me know.

2

In reply to Akhil Mehta:

https://verificationacademy.com/forums/systemverilog/overlapped-implication-and-nonoverlapped-imlplication

3

In reply to Akhil Mehta:
As a beginner in SVA, there are many concepts that you need you thoroughly understand, with the use of implication being one of them. Other concepts include threading and the application sequence and property operators. I STRONGLY suggest that you read my papers that touch on these topics:
Papers:

Ben Cohen