Overlapped implication and nonoverlapped imlplication

SystemVerilog
,
1

What is the difference between
a|-> ##1 b;
and
a|=> b;
?

2

In reply to dip0:

I believe they are functionally identical in this case.

3

In reply to Richard Hamer (EnSilica):

I wonder then why SV has this |=> operator when things can be done by using |-> operator.

4

In reply to dip0:

Because it is not always followed by ##1. Sometimes you need to perform other checks in this same cycle.

5

In reply to Richard Hamer (EnSilica):

F.3.4.3.3 Derived nonoverlapping implication operator
— (R |=> P) is equivalent to ((R ##1 1) |-> P).
— (S |=> Q) is equivalent to ((S ##1 @(1) 1) |-> Q).

6

In reply to ben@SystemVerilog.us:

LRM 1800-2012 says

sequence_expr |=> property_expr

is equivalent to the following:

sequence_expr ##1 `true |-> property_expr