How to connect the inout port of class interface to inout port of module

SystemVerilog
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1

In the below code, I am trying to connect the inout port member(data) of virtual interface(device_if) from device class to the inout port(data) of device_top module using “tran” keyword. But it is not working.

As per my knowledge, the possible ways of making the inout port connection for above case are,

  1. Instead of declaring signals on the device_top module port list, we can declare device_if interface on the module port list and make interface connection to class vif.
    Or
  2. In the device_top module, depending on the cmd and cmd_enable signals, identify the data direction and assign the values accordingly on inout port.

But, How can I do direct connection of inout port signal without adding device_if declaration on device_top module or depending on the data direction?

Thanks.

Code:

timescale 1ps/1ps
interface device_if(input clk, input reset);
  logic       cmd_enable;
  logic       cmd;
  wire [7:0]  data;
  
  logic [7:0] data_reg = 'z;
  assign data = data_reg;

  modport dev(
    input   cmd_enable,
    input   cmd,
    input   data,
    output  data_reg
  );

  modport host(
    output  cmd_enable,
    output  cmd,
    inout   data
  );
endinterface

class device;
  virtual interface device_if.dev vif;
  bit[7:0] mem;

  task run();
    forever begin
      @(posedge vif.clk);
      if(vif.reset == 0 && vif.cmd_enable == 1 && vif.cmd == 1/*WRITE*/) mem <= vif.data;
      else if(vif.reset == 0 && vif.cmd_enable == 1 && vif.cmd == 0/*READ*/) vif.data_reg <= mem;
    end
  endtask
endclass

module device_top(input clk, input reset, input cmd_enable, input cmd, inout data); // we must have these inout/input signals in the port list and must not declare device_if interface in the  port list
  device_if dev_if;

  assign dev_if.cmd           = cmd;
  assign dev_if.cmd_enable    = cmd_enable;
  **//tran(data, dev_if.data); // not working. How to connect interface inout signal to module port inout signal?**

  device dev;
  initial begin
    dev = new();
    dev.vif = dev_if;
    dev.run();
  end
endmodule
2

In reply to vadivelan014:

See replies and links in
https://verificationacademy.com/forums/systemverilog/assigning-interface-net-type-signals-class

3

In reply to vadivelan014:
Please use code tags making your code easier to read. I have added them for you.

4

In reply to ben@SystemVerilog.us:

Hi Ben,
Thanks for sharing link, the info is helpful. I have tried multiple iterations to make the inout port connection working with simple declarations like it was done for input/output signals.

 So, instead of using "tran" keyword for inout connection, I have used two separate assign statements to connect the interface inout signal to module port inout signal on write and read direction respectively. This resolves my issue. Given Below the working code snippet.

Thanks.

Working Code:

`timescale 1ps/1ps
interface device_if(input clk, input reset);
  logic       cmd_enable;
  logic       cmd;
  logic [7:0] addr;
  wire  [7:0] data;
  
  logic [7:0] data_reg = 'z;
  assign data = data_reg;

  modport dev(
    input   clk,
    input   reset,
    input   cmd_enable,
    input   cmd,
    input   addr,
    input   data,
    output  data_reg
  );

 // modport host(
 //   output  cmd_enable,
 //   output  cmd,
 //   inout   data
 // );

  typedef enum bit[1:0] {NOP, READ, WRITE} command_t;
  command_t cmd_enum;

  assign cmd_enum = cmd_enable ? (cmd ? WRITE : READ) : NOP;
endinterface

class device;
  virtual interface device_if.dev vif;
  bit[7:0] mem [bit[7:0]];

  task run();
    forever begin
      @(posedge vif.clk);
      if(vif.reset == 0 && vif.cmd_enable == 1 && vif.cmd == 1/*WRITE*/) mem[vif.addr] = vif.data;
      else if(vif.reset == 0 && vif.cmd_enable == 1 && vif.cmd == 0/*READ*/) vif.data_reg <= mem[vif.addr];
      else vif.data_reg <= 'z;
    end
  endtask
endclass

`timescale 1ps/1ps
module device_top(input clk, input reset, input cmd_enable, input cmd, input logic [7:0] addr, inout [7:0] data); // we must have these inout/input signals in the port list insead of declaring device_if interface in the  port list
  device_if dev_if(clk, reset);

  assign dev_if.cmd           = cmd;
  assign dev_if.cmd_enable    = cmd_enable;
  assign dev_if.addr          = addr;

  //tran(data, dev_if.data); // NOT WORKING!!  How to connect interface inout signal to module port inout signal?
  assign dev_if.data          = data; // WORKING!!! wr data from host transfered to device
  assign data                 = dev_if.data_reg; // WORKING!!! rd data from device transfered to host

  device dev;
  initial begin
    dev = new();
    dev.vif = dev_if;
    dev.run();
  end
endmodule