Hi Guys,
In the beginning of simulation, Clock is changing from X to 0. which is causing “always@(negedge clk)” block triggering and assertion is wrongly triggered.
How to discard above said negedge triggering ?
I tried $isunknown(clk) as below, but no use.
input clk,ares;
reg op;
always@(negedge clk)
op = ares & !($isunknown(clk))
Thx
Ram
In reply to ramananda:
Hi Ramananda,
As per my understanding, when simulation gets started clock will be going from X to 0 but at this point, reset will remain asserted(which will indicate chip is not properly initialized or is getting initialized). correct? and after reset is de-asserted, clock will become stable. So above code can be modified as below,
input clk,ares;
reg op;
always@(negedge clk) begin
if(!reset) begin
//your code
end
end
Regards,
Priyank
In reply to Agrawal Priyank:
Hi Priyank,
This code itself is to findout the reset activity. ( There should not be any clock edge (pos/neg) when reset is asserted. )
in my case, reset apply and clock transition from X to 0 happening exactly at same time, causing my assertion to failure.
In reply to ramananda:
Hi,
You can change your clock generation logic to avoid negedge at Zero time.
// Use bit for zero initialized value of Clock
// to avoid initial X to Zero transition
bit clk; //Alternatively reg clk = 0; or reg clk = 1;
initial
begin
forever
#CLOCK_PERIOD clk = ~clk;
end
Issue resolved by comparing with old value.
assign #1 clk_is_invalid = $isunknown(clk);
always @(posedge clk) begin
op <= (ares==1 && !clk_is_invalid);
end
In reply to ramananda:
Declaring clk as a bit would have been much simpler and give you better performance.
or make a continuous assignment to a bit
bit _clk;
assign _clk = clk;
always @(negedge _clk)
op <= ares;
In reply to dave_59:
Hi dave_59,
Could you kindly explain the reason, why it can be work? I’m curious about that. Thank you so much.