How to bypass clock change from x to 0

SystemVerilog
,
2

In reply to ramananda:

Hi Ramananda,

As per my understanding, when simulation gets started clock will be going from X to 0 but at this point, reset will remain asserted(which will indicate chip is not properly initialized or is getting initialized). correct? and after reset is de-asserted, clock will become stable. So above code can be modified as below,


input clk,ares;
reg op;
always@(negedge clk) begin
  if(!reset) begin
    //your code
  end
end

Regards,
Priyank