To Check clock alignment using system verilog assertion

SystemVerilog
, , ,
1

Hi,

I have in_clk and in_clk_b(both are compliment to each other)clocks and clk_out_enable signal and the output signal is clk_out ( another clock)
How can i write a system verilog assertion to check clk_out is edge aligned with in_clk and in_clk_b when clk_out_enable signal is high?

Thanks in advance,
Praveen

2

In reply to praveen1705:
Modify the following code as needed.


/* I have in_clk and in_clk_b(both are compliment to each other)clocks and 
   clk_out_enable signal and the output signal is clk_out ( another clock)
How can i write a system verilog assertion to check clk_out is edge aligned 
    with in_clk and in_clk_b when clk_out_enable signal is high? */ 
    // So 
    module top;
        timeunit 1ns / 100ps;
        `include "uvm_macros.svh"
        import uvm_pkg::*;
        bit in_clk, clk_out, enb=1, a, b;
        initial forever #10 in_clk = !in_clk;
        property p_aligned; 
            realtime t; 
            @(posedge in_clk) (enb, t=$realtime) |-> 
                       @(posedge clk_out)  ($realtime -t) <=1.2ns;
        endproperty 
        ap_aligned: assert property(p_aligned);  
        
        initial begin
            bit[2:0] v, v2;
           repeat (200) begin
             @(in_clk);
             if (!randomize(v) with {
               v  dist {0:= 1,     1 := 1,   2 := 1};
             })
               `uvm_error("MYERR", "This is a randomize error");
             v2=v*1.1ns;
            #v2 clk_out =!clk_out; 
           end
           $finish;
         end
      endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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3

In reply to ben@SystemVerilog.us:

Thanks Ben, Modified the code as per my specifications and it got worked.

Could you please let me know what this if block is doing?
if (!randomize(v) with {
v dist {0:= 1, 1 := 1, 2 := 1};
})

4

In reply to praveen1705:

if (!randomize(v) with {
v dist {0:= 1, 1 := 1, 2 := 1};
Creates a weighted randomized number with values of 0,1,2. Here they are equal weights.

if (!randomize(v) with {
v dist {0:= 1, 1 := 3, 2 := 0};
Here, value 2 never occurs, 1 occurs 3/4th the time, and 0 occurs 1/4th the time.

5

In reply to ben@SystemVerilog.us:

Thanks Ben

6

In reply to ben@SystemVerilog.us:

what are we trying to check here?
Are we checking that one of the output clock edges aligns with one of the input clock edges(could be any edge pos with neg /neg with pos)?

Can you help explaining more on the check below. We saved the time when the input clock rising edge was detected in the antecedent but how to arrive at the math for the clk_out part as we are randomizing the multiplier and also can pick any clock period for output clock.


@(posedge clk_out)  ($realtime -t) <=1.2ns;