In reply to praveen1705:
Modify the following code as needed.
/* I have in_clk and in_clk_b(both are compliment to each other)clocks and
clk_out_enable signal and the output signal is clk_out ( another clock)
How can i write a system verilog assertion to check clk_out is edge aligned
with in_clk and in_clk_b when clk_out_enable signal is high? */
// So
module top;
timeunit 1ns / 100ps;
`include "uvm_macros.svh"
import uvm_pkg::*;
bit in_clk, clk_out, enb=1, a, b;
initial forever #10 in_clk = !in_clk;
property p_aligned;
realtime t;
@(posedge in_clk) (enb, t=$realtime) |->
@(posedge clk_out) ($realtime -t) <=1.2ns;
endproperty
ap_aligned: assert property(p_aligned);
initial begin
bit[2:0] v, v2;
repeat (200) begin
@(in_clk);
if (!randomize(v) with {
v dist {0:= 1, 1 := 1, 2 := 1};
})
`uvm_error("MYERR", "This is a randomize error");
v2=v*1.1ns;
#v2 clk_out =!clk_out;
end
$finish;
end
endmodule
Ben Cohen
http://www.systemverilog.us/
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- SVA in a UVM Class-based Environment
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