In reply to praveen1705:
Modify the following code as needed.
/* I have in_clk and in_clk_b(both are compliment to each other)clocks and
clk_out_enable signal and the output signal is clk_out ( another clock)
How can i write a system verilog assertion to check clk_out is edge aligned
with in_clk and in_clk_b when clk_out_enable signal is high? */
// So
module top;
timeunit 1ns / 100ps;
`include "uvm_macros.svh"
import uvm_pkg::*;
bit in_clk, clk_out, enb=1, a, b;
initial forever #10 in_clk = !in_clk;
property p_aligned;
realtime t;
@(posedge in_clk) (enb, t=$realtime) |->
@(posedge clk_out) ($realtime -t) <=1.2ns;
endproperty
ap_aligned: assert property(p_aligned);
initial begin
bit[2:0] v, v2;
repeat (200) begin
@(in_clk);
if (!randomize(v) with {
v dist {0:= 1, 1 := 1, 2 := 1};
})
`uvm_error("MYERR", "This is a randomize error");
v2=v*1.1ns;
#v2 clk_out =!clk_out;
end
$finish;
end
endmodule
Ben Cohen
http://www.systemverilog.us/
For training, consulting, services: contact
http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
...
1) SVA Package: Dynamic and range delays and repeats
https://rb.gy/a89jlh
2) Free books: Component Design by Example
https://rb.gy/9tcbhl
Real Chip Design and Verification Using Verilog and VHDL($3)
https://rb.gy/cwy7nb
3) Papers:
- Understanding the SVA Engine,
https://verificationacademy.com/verification-horizons/july-2020-volume-16-issue-2
- SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue
- SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment