All ports are available in your toplevel module. And these port signals are driven by the uvm_drivers. You can also drive the reset in your env. But you should not do this from an initial block in your toplevel module. This might not be coordinated with the function of thhe whole environment.
instead of controlling reset from tb top, i want to do it through seq item. But somewhere i am missing out the connection. Could someone check that link and help me out??
This is one of the issues. The second one is rst is not rand in the seq_item definition.
And then you have to refine your driver with respect to the reset. the Reset function is mot usefula as it is now.
I tried giving reset through seq item. but im missing out the logic in refining driver according to that. Can you tell how am i supposed to change the driver logic?
i did that. The output is correct. but in my waveform, the in, out and states are not starting from 0. They start from 4ns.am not able to attach a screenshot of the waveform here.
Yes, it is. You can’t see the seq_items in the waveforms. There you see only the signals/variables. Because you are using logic as data type you see the x. logic is initialized to x.
Thanks for your help and suggestions. Im thinking about using $root to control reset from tb top itself. In that case, how the driver logic should be changed?
If you are replazing the logic data type by bit you’ll see the 0 instead of x. Another wa is to initialize your values to z. But what you have is completely fine.
I think you have seen in is 0 from the beginning and out and state is x. This comes from your design.Simple Verilog does not know 2-state variables. There is the type reg used.