UVM

UVM
47

In reply to Muthamizh:

Any possible help for me??

48

In reply to Muthamizh:

instead of controlling reset from tb top, i want to do it through seq item. But somewhere i am missing out the connection. Could someone check that link and help me out??

49

In reply to Muthamizh:

This is one of the issues. The second one is rst is not rand in the seq_item definition.
And then you have to refine your driver with respect to the reset. the Reset function is mot usefula as it is now.

50

In reply to chr_sue:

I tried giving reset through seq item. but im missing out the logic in refining driver according to that. Can you tell how am i supposed to change the driver logic?

51

In reply to Muthamizh:

Please look here and compare with your code.

52

In reply to chr_sue:

i did that. The output is correct. but in my waveform, the in, out and states are not starting from 0. They start from 4ns.am not able to attach a screenshot of the waveform here.

53

In reply to Muthamizh:

They are starting from 0, but with undefined value (x). The data are synchronous with your clock.

54

In reply to chr_sue:

Is that correct? Cant i make it to start it from 0? nd why is it starting from x?

55

In reply to Muthamizh:

Yes, it is. You can’t see the seq_items in the waveforms. There you see only the signals/variables. Because you are using logic as data type you see the x. logic is initialized to x.

56

In reply to chr_sue:

Thanks for your help and suggestions. Im thinking about using $root to control reset from tb top itself. In that case, how the driver logic should be changed?

57

In reply to Muthamizh:

If you are replazing the logic data type by bit you’ll see the 0 instead of x. Another wa is to initialize your values to z. But what you have is completely fine.

58

In reply to chr_sue:

i have changed it to bit. Still it starts from x. Then it is not the correct one, right??

59

In reply to Muthamizh:

You have to do this in the interface definition.

60

In reply to chr_sue:

i did it in interface only.

61

In reply to Muthamizh:

I think you have seen in is 0 from the beginning and out and state is x. This comes from your design.Simple Verilog does not know 2-state variables. There is the type reg used.

62

In reply to chr_sue:

Yes in is 0 from the beginning. Thank you so much for your suggestions. They were very helpful and useful. Thanks again.

63

In reply to Muthamizh:

What is phase objection actually?

64

In reply to Muthamizh:
What do you mean with phase objection?

The objection mechanism is used stop the simulation after completing all sequences and run_phase tasks.
If you do not implement this mechanism the simulation stucks at time 0.
You can implement the objections in different objects (components, sequences).

65

In reply to chr_sue:

This is what i wanted to know. Thank you for the explanation.

66

In reply to Muthamizh:
Now i need to do another testcase for the same fsm. i need to stop the clock generation and check the response. How to do that? Any idea please?