Reuse constraints in child classes

UVM
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1

Hi all,

I have a UVM testbench with following classes and need your suggestions to overcome the problem I’m facing.


class register_model extends uvm_reg_block;
rand reg_set_1 reg_1;
rand reg_set_2 reg_2; //This is a replica of reg_set_1 but with a different base address and is added newly

build();
endclass : register_model

class custom_reg_model extends register_model;

//constraints on reg_1 to control the randomization of register values
constraint enable_value
{
  reg_1.enable.value == 1;
}
endclass : custom_reg_model

uvm_reg_block reg_set_2 is added recently and is a replica of reg_set_1. I need all the constraints I wrote for reg_set_1 to be applicable for the new reg_block(reg_set_2) as well.
What would be the recommended way to handle this scenario?

I tried the following but I’m not able to get the required behaviour:

  1. Create multiple instances of custom_reg_model and use factory override(set_inst_override_by_type) to override reg_model_1 with reg_model_2 based on the instance name. In this way each instance of the custom_reg_model will be responsible for a particular reg_block. Since reg_model_2 is not extended from reg_model_1, this approach didnt work.
  2. Second approach I had in my mind was to make the class custom_reg_model parametrized by passing the type while we create multiple instances. But effort wise, this is not easy to accomodate as current testbench doesnt have parametrized classes
  3. Another approach was to develop a custom copy method so that a dummy handle in custom_reg_model will do the randomization and copy the contents to appropriate reg_blocks based on the instance ID. I terribly failed to execute this as I didnt find a method to set the register values back to a handle. I used reg_1.get_registers(registers) to get all the registers. But didnt find any such method to set the registers to another reg_block. Any suggestions on this approach are welcome.

Thanks,
SV_UVM_49

2

In reply to sv_uvm_49:

I believe you are making your problem more complicated as it is. Why do you want to override registers in your reg model.
The registers of the register model can be considered as objects which can store certain values. Filling in different data to your registers or fields will be done using sequences and seq_items. When generating the sequence items you can add the constraints to the randomization process. This is how you can restrict values in your registers.