How to instantiate verilog module in uvm driver

UVM
1

hai,
we are not able to instantiate verilog module in uvm driver. but to drive inputs for ddr in the static test_bench we will genrate a verliog module from the core that module in static testbench we are instatiating and then driving inputs.
in uvm how can i use that module generated from core. here we r not able to instatiate right?

2

In reply to nana:

You cannot instantiate a module in a class. But in my eyesit does not make sense to instantiate a verilog module in a uvm_driver, because your module does not have a TLM interface. But what should be useful is to reuse a driving task from your module (if there is one) in the uvm_driver.

3

In reply to nana:

Hi,
You can instantiate your Verilog file in a SV interface and then call the corresponding task in your UVM based driver.

Ting

4

Thank you for yours reply chr_sue and ting.

if we instantiate module once in interface then why we have to call again from driver.

5

In reply to nana:

I guess the module in the interface contains tasks or functions. This is there only a definition. These methods have to be called from another place.

6

In reply to nana:

The reason to make the task called by the drive is you might want to control it through a sequence in your UVM env. Maybe the new tests were all uvm based and wanted to control when the task inside of legacy module to be invoked.

7

In reply to nana:
You may want to see this thread.

8

thank you for yor rply chr_sru,ting amd dave