Zero delay loop in verilog design

UVM
1

** Error: (vsim-3601) Iteration limit reached at time 530 ns.

This is a zero-delay loop

i am running the test case in UVM to verify the core.

The core have accumulator,instruction decoder and ALU.
The ALU is getting the first data only. While coming to second the instruction , the simulator is getting the error like this
Simulator :model sim

** Error: (vsim-3601) Iteration limit reached at time 530 ns.

This is a zero-delay loop:

Please suggest me about this issue to rectify…

2

You may need to increase the value of the IterationLimit variable.

Check the User Manual section “Detecting Infinite Zero-Delay Loops”

3

In reply to dave_59:

I checked the User Manual section and increase the Iteration Limit 5000 to 6000 in modelsim simulator, but i am getting same error.

4

In reply to santhosh1626:

There were a few other suggestions such as switches and breakpoints to try. Try increasing the limit a few orders of magnitude as well.

5

In reply to dave_59:

Hi,
I also face this error.

** Error (suppressible): (vsim-3601) Iteration limit 5000 reached at time 0 ps

In modelsim.ini → I changed IterationLimit from 5k to 9k and it got resolved.

However, for my curiosity I debug further by
Re-run vopt with +acc to open full visibility to the design.
Re-run vsim with +autofindloop.

And these options are very useful to figure out that which file is troubling for zero delay infinite loop from my simulation log file.

This is a zero-delay loop:

/tb_top/pcie_if_rc/#INITIAL#62361 /xyz/abc/mentor/questa_vip/10.3c.1.p1/ovm/questa_mvc_src/sv/pcie//shared/pcie_interfaces_MTI.svh:62367

From this message, I got to know that I am compiling two different version of PCIe VIP at the same time (10.3c.1.p1 is not the one I wanted to use) and I took corrective action (compile intended VIP, not both at the same time). Later I kept IterationLimit set back to 5k.