Working of bind construct

SystemVerilog
,
1

From assertion perspective ::

’ bind ’ allows us to keep design logic separate from the assertion logic . Designers do not like to see anything in RTL that isn’t going to be synthesized . ’ bind ’ helps in that direction

Consider following code ::


module  designmodule  ( da , db , dclk );
  input   da , dclk ;
  output  logic  db;
  always @( posedge dclk )  db <= da;
endmodule

module  propertymodule ( pa , pb , pclk );
  input  pa , pb , pclk ;

  property  rc1;
    pa |=> pb ;
  endproperty

  baseP:assert  property ( @( posedge pclk )  rc1 )  else  $display($time , " property  fails ");
endmodule

[Q1] What’s the difference between following 2 Scenarios ::


//  Scenario1  ::  Using  bind
module  tb1;

 bind  designmodule  propertymodule  dpM ( .pa( da ) , .pb( db ) , .pclk( dclk ) );

endmodule

//  Scenario2  ::  Without  bind
module  tb2;
 logic  ta , tb , tclk;

 designmodule  DM  ( .da(ta) , .db( tb ) , .dclk( tclk ) ) ;

 propertymodule  PM ( .pa( ta ) , .pb( tb ) , .pclk( tclk ) );

endmodule

One possible answer is Scenario2 applies to only specific instance of designmodule whereas with Scenatio1 applies to every instances of designmodule .

[Q2] Are there any further differences between the two ?

 **Significance  of  instance  created  by  ' bind '  construct  ::**

  Within  Scenatio1 ,  an  instance  of  propertymodule  named  ' dpM '  is  created  by  default  within  every  instance  of  designmodule .

  By  default  in  Verilog  a  module  declaration  in  itself  doesn't  do  anything ( unless it's top_tb ) , one  needs  to  instantiate  it  for  the  logic  defined  within  it  to  work . 

  Hence  simply  declaring  propertymodule  doesn't  do  anything , one  needs  to  create  an  instance  of  propertymodule  for  the  assertions to  execute .  

  bind  construct  creates  the  instance  of  propertymodule  for  the  assertions  to  trigger . 

  This  explains  the  significance  of  instance  name  created  by  bind  construct  for  assertion  based  logic .

  **[Q3] For  non-assertion  based  module / interface  what's  the  significance  of  the  instance  name  ?**
2

In reply to Have_A_Doubt:

  1. The bind is a better approach because your verification module can easily access signals that are internal to the design. When you bind, you are like instantiating the VF module inside the design module.
  2. Use the SVG module interface syntax instead of the Verilog approach; it is more readable.
  3. Use the same variable name throughout. Your da, pa stuff is confusing, particularly whne debugging. It will drive you crazy to continually convert one for the other.

module  designmodule  (input bit da, dclk, output bit db);
  always @( posedge dclk )  db <= da;
  bit a, b; // used internally in the desing and are not IO
  int count; 
  always @( posedge dclk) if(da) count <= count+1; 
endmodule
 
module  propertymodule ( input bit da , db , dclk, a, b, int count); 
  property  rc1;
    da |=> db ;
  endproperty
 
  baseP:assert  property ( @( posedge dclk )  rc1 );

ap_Count: assert property(@(posedge dclk) da |-> ##1 count==$past(count) +1);
endmodule


//  Scenario1  ::  Using  bind
module  tb1;
 
 bind  designmodule  propertymodule  dpM
  ( .da(da), .db(db),.dclk(dclk), .a(a), .b(b), .count(count));
 
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

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