In reply to ben@SystemVerilog.us:
Thanks Dave for clarifying this issue.
The LRM says in many places that A net cannot be procedurally assigned. (6.5 Nets and variables) Table 10-1—Legal left-hand forms in assignment statements
An the LRM says that 23.3.3.2 Port connection rules for variables
— A variable data type is not permitted on either side of an inout port.
Therefore you cannot make a procedural assignment to an inout port
In reply to ben@SystemVerilog.us:
Here is a simple example of what ben is trying to say
ex1: [Net type cannot be used on the left side of this assignment]
wire x // not allowed needs to be logic
initial x <= 1;
ex2 [Non-net variable ‘x’ cannot be an inout port]
module x(inout logic x); // not allowed, needs to be net type
endmodule
In reply to ben@SystemVerilog.us:
Hi Ben,
I have just started learning uvm.
Can you tell me what do you mean by this?
virtual interfaces come into play when using classes to defer at a later stage the definition of the physical interface to the one being worked on in the class.
In reply to pghosh:
See my example above from November 20, 2013 at 10:35 am
Basically, since the interface is “virtual” and not physically real, you can connect it to any real physical interface at a later stage. Think of it as a power plug to your toaster; that “plug” is really useless because it does not connect to a power 110 or 220 power source. However, during the fabrication of the toaster, you create a cord and a power plug without knowing which socket it will be connected to. Therefore, until it is connected to a “real” socket, you can tune to the toaster and the design of that plug (e.g., 3 plug, 2 plug, USA design, European design).
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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In reply to dave_59:
Hi dave
as above explain for dynamic class if we want use interface we need to use keyword virtual.I want to know exactly what “virtual” keyword does so that interface can easily use in classes.