In reply to mallick1:
I can’t easily locate where in 1800 those rules are defined. However, with 2 separate simulators, I get the same errors for the following code:
module ld_reg #(SIZE=8)
(input logic clk, ld,
input logic[SIZE-1:0] d_in,
output logic[SIZE-1:0] r_out, d_out,k_out,
inout logic[SIZE-1:0] data1, data2, data3);
logic a, b=1'b1, oe; // local variable
wire[SIZE-1:0] wdata1, wdata2, wdata3;
always @ (posedge clk) begin : FF_LD
// The begin statement is only needed
// if multiple statements in body of always
r_out <= d_in;
data3 <= d_in; // **** illegal LINE 13
// line above: A net is not a legal lvalue in this context
// wdata1 = d_in; // illegal
// line above: A net is not a legal lvalue in this context
//assign wdata3 = 'bZ; // illegal
assign d_out=oe ? 8'b101_1110 : 'bZ;
end : FF_LD
task is_illegal;
@ (posedge clk)
data1 <= d_in; // **** Illegal reference to net "data1". line 23
wdata1 <= d_in; // Illegal reference to net "wdata1".
endtask
// assign data1 = oe ? 8'b101_0000 : 'bZ;
assign k_out=8'b10X_XZZ0;
endmodule : ld_reg
// COMPILATION RESULTS:
# ** Error: ld_reg.sv(13): Illegal reference to net "data3".
#
# ** Error: ld_reg.sv(23): Illegal reference to net "data1".
#
# ** Error: ld_reg.sv(24): Illegal reference to net "wdata1".
Ben