In reply to ben@SystemVerilog.us:
Thanks Dave for clarifying this issue.
The LRM says in many places that A net cannot be procedurally assigned. (6.5 Nets and variables) Table 10-1—Legal left-hand forms in assignment statements
An the LRM says that 23.3.3.2 Port connection rules for variables
— A variable data type is not permitted on either side of an inout port.
Therefore you cannot make a procedural assignment to an inout port