Why do we need virtual interfaces in system verilog?

SystemVerilog
22

In reply to ben@SystemVerilog.us:

Here is a simple example of what ben is trying to say

ex1: [Net type cannot be used on the left side of this assignment]
wire x // not allowed needs to be logic
initial x <= 1;

ex2 [Non-net variable ‘x’ cannot be an inout port]
module x(inout logic x); // not allowed, needs to be net type
endmodule