Why base class can't be assigned to derived class?

SystemVerilog
, ,
3

In reply to ben@SystemVerilog.us:

Thanks Ben,

My Query relates to the inheritance concept of OOPs.

If no extra properties defined in derived class, why compiler still complains about legal assignment.

class A;
  bit var1;
endclass
 
class B extends A;
  
endclass
 
module top;
  A a =new();
  B b =new();
  initial
    b = a; // Compilation error
endmodule

–SMS