Why base class can't be assigned to derived class?

SystemVerilog
, ,
2

In reply to SMS:


class A; // Base class
  bit var1;
endclass
 
class B extends A;
  bit b1;
endclass
 
module top;
  A a =new();  // pointer to base 
  B b =new(); // pointer to B, with access to a vars 
  initial begin 
    b = a; // Compilation error
          // if it were legal, then b points to the base class A
    b.b1=1'b1; // There would be no "b1" since the pointer b has no access to 
               // the variables in class b (b pointer is to the base class)     
  end 
endmodule

Ben SystemVerilog.us