Which HDL has probability of consuming more simulation time between SV and Verilog?

If I am having a code in both in SV and verilog (consider equal number of code lines),which will take more simulation time when I run it?

In reply to bachan21:

If its like same code, I don’t believe there is a difference.
If the SystemVerilog code contains structures and libraries not available in what is known as ‘Verilog’, then expect a slowdown.

Ben systemverilog.us

In reply to bachan21:

You cannot judge performance simply by lines of code, even within the same language.

Even with this simple statement

if (A==B) ...

Without knowing the datatypes behind A and B, the performance could be wildly different.

In reply to dave_59, ben@SystemVerilog.us:
SystemVerilog has more event regions compared to Verilog. So that was the thought in my head when I asked this question. I assumed that SystemVerilog may get bit slower on this basis. But complexity of data may differ between them. So I think it is not possible to get into a perfect conclusion on which will be faster even for same set of code. Correct me if I am wrong.

In reply to bachan21:

Is there such a pure Verilog simulator tool today?
I maybe wrong, but why would a vendor support only Verilog, or Old Verilog and SystemVerilog? For backward compatibility, SystemVerilog supports the old style of Verilog interface.
I suppose that one can use a very old version of a Verilog tool. However, with evolution software and cloud services I presume that SystemVerilog newer versions might be more efficient.

In reply to bachan21:

I could see compilation and optimization processes might take a little longer because extra complexities in choices.

If you’re seeing simulation differences between the same code interpreted as Verilog versus SystemVerilog, you will have to take that up with your tool vendor. Event-based simulators typically skip to the next scheduled event and nothing get executing in between.