In reply to dave_59, ben@SystemVerilog.us:
SystemVerilog has more event regions compared to Verilog. So that was the thought in my head when I asked this question. I assumed that SystemVerilog may get bit slower on this basis. But complexity of data may differ between them. So I think it is not possible to get into a perfect conclusion on which will be faster even for same set of code. Correct me if I am wrong.