What is the exact difference between static tasks/functions and automatic tasks/functions ? please explain with a clear example

SystemVerilog
30

In reply to abajaj:

module automatic test();
 
task add(int a, int b); // the lifetime of this task is now implicitly automatic
	#2;
	$display("the sum is %0d", a+b);
endtask
 
initial
	fork
		begin
			add(2,3);
		end
		begin
			#1;
			add(3,4);
		end
	join
endmodule