In reply to dave_59:
Hi Dave, thank you for your explanation. I am wondering more about the synthesis consequences of automatic vs static and what later enabled automatic? Specifically, it is my understanding that each call of a module, task, or function in a verilog program will synth into a hardware element or collection of for each.
Let’s say I have a fibonacci program with 20 rounds. For example, let’s say each round synthesizes to a single CLB such that I now have 20 CLBs utilized on the fpga to execute the entirety of the program. this would mean that each round is static in terms of it’s hardware implementation right? Automatic would be if I only had 1 or a few CLBs that could be reused over and over as many rounds as it takes to execute a program? I hope you can see my confusion. It hovers around how static and automatic are thought about in terms of synthesis, not programming.
Thanks Again!