What is the exact difference between static tasks/functions and automatic tasks/functions ? please explain with a clear example

SystemVerilog
27

SystemVerilog added a lifetime qualifier for modules and interfaces so that all routines defined in that module would be considered automatic by default so you didn’t have to add the automatic keyword after each function or task declaration.

Does that mean, by Default all functions and tasks are Automatic ?

I tried the example

module test();
 
task add(int a, int b);
	#2;
	$display("the sum is %0d", a+b);
endtask
 
initial
	fork
		begin
			add(2,3);
		end
		begin
			#1;
			add(3,4);
		end
	join
endmodule

whose o/p is 7 ,7 which means by default lifetime is static …