What is the exact difference between static tasks/functions and automatic tasks/functions ? please explain with a clear example

SystemVerilog
15

In reply to puttasatish:

Can anyone please explain me

module test();
 
task add(int a, int b);
	#2;
	$display("the sum is %0d", a+b);
endtask
 
initial
	fork
		begin
			add(2,3);
		end
		begin
			#1;
			add(3,4);
		end
	join
endmodule

How do we get sum is 7
Sum is 7
According to me, it should be 5 and 7, but for what reason the sum 7 and 7