What is the difference between @(posedge clk) begin end.... and @(posedge clk);?

SystemVerilog
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6

I Think It should work exactly the same from the test bench point of view.
In the first code snippet, the statements inside the begin…end will get triggered at the posedge.

While in the second case, they get triggered 0 time units after the posedge which means the same thing.

Regards,
Durgesh