What is the difference between @(posedge clk) begin end.... and @(posedge clk);?

SystemVerilog
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10

In reply to dave_59:

Hi Dave,

Thanks for the answer. :)

What if the code is like this:

// In the testbench driver
#1 signal = 1;
#1 signal = 0;

// In the testbench monitor
@(posedge clk) begin
if(signal) $display(“signal asserted”);
end

In which timestamp does the “signal asserted” will appear? Is it at the same time with the posedge? Or after 1 clock cycle?
I’m asking this because in RTL a register can only sample the signal after 1 clock cycle, not at exactly the same time with the posedge.

What I want my testbench to do is to report only at the time the RTL registers actually see the signal.