In reply to Reuben:
This is a completely different question, but again you have not show enough code to explain. When is the signal written in relation to the time of the posedge clk?
If you have multiple processes where one process is writing to a signal (the driver), and another process is reading the same signal (the monitor) at the same time, then you have a race condition in that you don’t know if you are reading the old value or newly written value of the signal. That is why we use non-blocking assignments (NBA) in Verilog. Search for that.