Sampling at posedge of clk

SystemVerilog
1

Hi ,
I have a scenario where whenever input intr is comes output signal named “wakeup” would becomes 1 in next clock and if intr is 0 output should be zero , for this i added check point in my test like below

fork 
begin
 while(1) begin
  @(posedge intr) begin
 `uvm_info("chk1");

  @(posedge clk);    //waiting for next clk
   `uvm_info("chk2");

   if(wakeup != 1)
     //ERROR 
   end
 end
end //process 1
begin
 while(1) begin
  @(negedge intr) begin
  `uvm_info("chk3");

  @(posedge clk);  //waiting for next clk
   `uvm_info("chk4");
   if(wakeup != 0)
     //ERROR
   end
  end
end //process 2

begin
#40000ns;
end //process-3
join_any

2 Observations:
1.Here with above code what i am observing is after posedge of intr only i am seeing chk1 but chk2 was seen before next clk edge
2.before negedge of intr from process-2 chk3 was seen and chk4 is coming after wakeup is zero but still check point is failing

Is adding this line @(posedge clk); will really waits untill next clock posedge ?

2

What is a “check point”? Are intr and wakeup asynchronous to clk? We need to know how they get assigned. Usually, you should not be using any other event controls other than @(posedge clk)

3

Hi Dave,

  1. Are intr and wakeup asynchronous to clk ? —> No . both are sync to posedge of clk
  2. you should not be using any other event controls other than `@(posedge clk) —> Then any other way we can check the feature
    Feature :
    Wakeup should be 1 in next clk when intr is one and wakeup should be zero in next clk when intr is 0
4

“begin” after @(posedge intr)? What does it means?

5

See What is the difference between @(posedge clk) begin end.... and @(posedge clk);? - #9 by dave_59

@venkateshk Try @(posedge clk iff intr)

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