What is 4KB address boundary in AXI protocol?

SystemVerilog
,
1

i am confusing , how to calculate this 4kb address boundary.

as specification suggests wrap address should not cross 4kb address boundary.

2

In reply to nup777:

Addresses that are multiple of 4KB (say 4096, 40962, 40963 and so-on) are termed as 4KB address boundaries. That is a burst transfer should always satisfy the following condition.
Start_Address % 4096 == (Start_address + (burst_size * burst_length)) % 4096

Examples:
**Valid incremental burst transfer:
**Starting Addr: 4080, burst_size = 4bytes, burst_length = 2. Ending address: 4088

**Invalid incremental burst transfer:
**Starting Addr: 8184, burst_size = 4bytes, burst_length = 3. Ending address = 8196. (burst transfer crossing 8192 (4kb address boundary))

A burst transfer should not cross a 4KB address boundary in AXI, as in this case portion of the burst targets one slave, and the rest of the transfer targets the next slave which is an impractical situation.

3

thanks for reply.

if we have multiple slaves , each slave can have 4kb boundary?

4

In reply to S.P.Rajkumar.V:

When I work out the calculation for the valid and invalid incremental burst transfer, I’m finding that they both don’t equal respectively as shown below.

Valid incremental burst transfer:
4080 % 4096 == ( 4080 + (4*3)) % 4096
4080 == 4096

Invalid incremental burst transfer:
8184 % 4096 == ( 8184 + (4*3)) % 4096
4088 == 4

Can you clarify this?
Thanks,
Mark

5

In reply to markylew:

The AXI spec (similarly in the PCIE spec) basically says that an atomic transaction (one AR, or AW transaction) may NOT cross a 4KB boundary. Said another way: define the addresses:

wire [ MSB : 0 ] start_ar_addr, end_ar_addr;

The atomic transaction is only valid if:

 wire assert_valid_transaction = start_ar_addr[ MSB : 12 ] == end_ar_addr[ MSB : 12 ];

Regards,

Mark

6

In reply to Mark Curry:

Thanks for clarifying this Mark.

I’m still looking at S.P.'s equation using modulo. Do you know what’s the correct way to use modulo to check the condition? I’m targeting an FPGA for my verilog and I’d like to know which code provides the optimum logic for resources/performance.

7

In reply to markylew:

Why insist on using the modulo operator? For most synthesis tools, this operator use is limited to constants of a power of two anyway - meaning the synthesis tool translates a modulus operations to “just look at this subset of bits”. i.e.

foo % 4096

Means to the synthesis tool - “Just look at foo[ 11 : 0 ]”. It’s easier, IMHO to just code it that way explicitly (or use a mask operation).

Most of the ways I’ve coded up a 4KB boundary check (for FPGA synthesis) is similar to what I wrote. It’s clear, concise, and synthesizable. Could someone code up a more clever, optimal version? Perhaps, but its such a tiny part of most designs, that this is usually a don’t care.

Clarity first should be the goal. Optimization is a secondary or even tertiary goal.

Rereading S.P.'s equation now I think it’s in error (or I’m not understanding the point being made)
Start_Address % 4096 == (Start_address + (burst_size * burst_length)) % 4096

In low level terms this is doing the OPPOSITE of what I wrote - this equations boils down to:

wire SP_assert_check = start_ar_addr[ 11 : 0] == end_ar_addr[ 11: 0 ];

Which doesn’t check the right thing.

Regards,

Mark

8

In reply to Mark Curry:

Thanks for the explanation and for confirming regarding S.P.'s equation.
It’s much appreciated!

Mark

9

In reply to markylew:

Small correction:
Start_Address / 4096 == (Start_address + (burst_size * burst_length)) / 4096

Instead of “%”, it should be “/”.

Please let me know in any case of conflict.