What is 4KB address boundary in AXI protocol?

SystemVerilog
,
5

In reply to markylew:

The AXI spec (similarly in the PCIE spec) basically says that an atomic transaction (one AR, or AW transaction) may NOT cross a 4KB boundary. Said another way: define the addresses:

wire [ MSB : 0 ] start_ar_addr, end_ar_addr;

The atomic transaction is only valid if:

 wire assert_valid_transaction = start_ar_addr[ MSB : 12 ] == end_ar_addr[ MSB : 12 ];

Regards,

Mark