VERIFICATION ASYNCHRONOUS FIFO CUMMINGS

SystemVerilog
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2

In reply to GiuseppeT:

I am completely new to the SystemVerilog world, and I am trying to verify the asynchronous FIFO made by Cummings.

In 2002 I wrote the book Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb That book includes Cumming async Fifo. It includes the following files:
bin2gray.v, gray2bin.v, graycntr.v, fifo_async.v, fifo_async_tb.v
If you need those files, let me know.

The goal is to verify this design by using the Tb components, so no UVM at all. I should basically focus on Generator (or sequencer), Driver, Interface, Monitor and Scoreboard.
There are at least 5 situations that I would like to verify which are: read only, write only, read/write at the same time, write when the FIFO is full, and read when the FIFO is empty.
Is it better to use two agents by splitting the write side and read side? If so, how can I realise the communication between the two of them when they need to provide the inputs and outputs to the monitor? Or is it better to use only one agent?

I would use one sequencer that based on the kind of transaction need would trigger the necessary task (e.g., read only, write only, delays, read & write, idle). The tasks will most likely include fork/join to execute the needed transactions and to store the write data into a queue. The interface should include assertions.

My original idea was to use a transaction with some constraints where I could use a 2-bit mode which is randomized and according to its value, I would have provided a specific stimulus (if mode =2’b00, then {winc, rinc} =2’b00 etc.) so that the Generator could just randomize all the inputs and eventually I should have at least 3 cases covered (write only, read only and write/read at the same time).
For the Write Full and Read Empty: I know the depth of the FIFO, and I would just declare a task that repeats itself one more time after the entire FIFO is filled and etc.

You have the right concepts. From my donated book A Pragmatic Approach to VMM Adoption
http://SystemVerilog.us/vf/VMM/VMM_pdf_release070506.zip
http://SystemVerilog.us/vf/VMM/VMM_code_release_071806.tar


class Fifo_xactn extends vmm_data; 
 import fifo_pkg::*; 
 rand fifo_scen_e kind; 
 rand word_t data; // in : data to push 
 rand int idle_cycles; 
 time xactn_time; 
 static vmm_log log = new("Fifo_xactn", //name 
 "class");6 // instance 
 constraint cst_idle { 
 idle_cycles inside {[1:3]}; 
 } 
 constraint cst_xact_kind { 
 kind dist { 
 PUSH := 400, 
 POP := 300, 
 PUSH_POP :=200, 
 IDLE := 300, 
 RESET := 1 
 }; 
 } // cst_xact_kind 
…
Figure 2.2.2.1-1

The point of this question is: is there any better way to proceed? Am I going in the wrong way? Maybe it’s because I am unexperienced, but by randomizing everything and telling the generator to generate, don’t know, 100 transactions, eventually every case will be covered I guess. Is a solution like this wrong?

I would use assertions in the interface to do the verification. The interface would include the queue for the storage of data. You can also write cover property statements to make sure that you covered the needed sequences.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

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