The rise and fall/rise of two signals are between 2 time margins

SystemVerilog
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1

Is there an OVL assertion to find out if the rise of a signal to the next rise of a signal duration is between 2 time values? The example I want to check that the rise of signal A to the next rise of signal A is between 100ns +/- 5ns.

2

In reply to VerifEx:

Check out the following link and modify it appropriately
https://verificationacademy.com/forums/systemverilog/checking-clock-period-using-system-verilog-assertion

Ben Ben@systemverilog.us

3

In reply to ben@SystemVerilog.us:

Once the signal gets asserted, I capture the current time, then I want to wait until the signal falls and make sure the delta time is between my min and max time. How do you do that comparison when it de-asserts?

property measure_rise_to_fall(bit clk, bit reset, bit sig_a, bit sig_b, time min_time, time max_time);
   time current_time;
   @(posedge clk) disable iff (reset) (($rose(sig_a),current_time=$realtime()) |=> $fell(sig_b) |=> ((min_time > ($realtime()-current_time)) & (max_time < ($realtime() - current_time)))); 

endproperty : measure_rise_to_fall
4

In reply to VerifEx:
In your requirements, I read the following:
Once the signal “a” gets asserted (i…e, $rose(a)), I capture the current time, then I want to wait until the signal**“b” falls (i.e., @(negedge b)**, which can be multiple clock periods (or less) of the @(posedge clk)) and make sure the delta time is between my min and max time. How do you do that comparison when it de-asserts?

Below are 2 solutions:

  • Solution using a task. Read my paper
    PAPER: Understanding the SVA Engine + Simple alternate solutions - SystemVerilog - Verification Academy
    Abstract: Understanding the engine behind SVA provides not only a better appreciation and limitations of SVA, but in some situations provide features that cannot be simply implemented with the current definition of SVA. This paper first explains, by example, how a relatively simple assertion example can be written without SVA with the use of SystemVerilog tasks; this provides the basis for understanding the concepts of multithreading and exit of threads upon a condition, such as an error in the assertion. The paper then provides examples that uses computational variables within threads; those variables can cause, in some cases, errors in SVA. The strictly emulation model with tasks solves this issue.
  • An assertion of same
    http://SystemVerilog.sv/fv/time_between.sv

// Once the signal gets asserted, I capture the current time, then I want to wait until the signal falls
// and make sure the delta time is between my min and max time.
//How do you do that comparison when it de-asserts?
import uvm_pkg::*; `include "uvm_macros.svh" 		
module top; 
	bit clk, a, b, c, rst;  
	default clocking @(posedge clk); endclocking
	initial forever #10 clk=!clk; 
	
	task automatic t_halffclk();
		automatic realtime t_then; 
		if($rose(a)) begin 
		  t_then = $realtime; 
		  // @(posedge clk) 
		  @(negedge b) a_time: assert(($realtime-t_then > 32ns)  &&
				                      ($realtime-t_then < 43ns) )   
			    $display("OK, negedge b =%t, delta=%t", $realtime, $realtime-t_then); else
		        $display("error, negedge b=%t, delta=%t", $realtime, $realtime-t_then);
		end
		else return; 		  
	endtask 
	
 
	always  @(posedge clk)  begin 
		t_halffclk();
	end 
	property measure_rise_to_fall(bit clk, bit reset, bit sig_a, bit sig_b, realtime min_time, realtime max_time);
		time current_time;
		@(posedge clk) disable iff (reset) 
			($rose(sig_a),current_time=$realtime)
			|=>  @(negedge b) ($realtime-current_time > min_time) && ($realtime-current_time < max_time); 
	endproperty : measure_rise_to_fall	
	ap_measure_rise_to_fall: assert property(measure_rise_to_fall( clk, rst, a, b, 32, 43));  
 
	initial begin 
		repeat(200) begin 
			@(posedge clk);   
			if (!randomize(a, c)  with 
					{ a dist {1'b1:=1, 1'b0:=3};
					  c dist {1'b1:=1, 1'b0:=1};
					}) `uvm_error("MYERR", "This is a randomize error")	
			if(c) #2 b=c; 
			else b=c; 
		end 
		$stop; 
	end 
endmodule    

  // simulation results
 OK, negedge b =                  90, delta=                  40
# OK, negedge b =                 230, delta=                  40
# error, negedge b=                 370, delta=                 100
# ** Error: Assertion error.
#    Time: 370 ns Started: 270 ns  Scope: top.ap_measure_rise_to_fall File: time_between.sv Line: 33 Expr: $realtime()-current_time<43
#    Local vars : current_time = 270
# ** Error: Assertion error.
#    Time: 370 ns Started: 350 ns  Scope: top.ap_measure_rise_to_fall File: time_between.sv Line: 33 Expr: $realtime()-current_time>32
#    Local vars : current_time = 350
# OK, negedge b =                 490, delta=                  40
# error, negedge b=                 710, delta=                  80
# ** Error: Assertion error.
#    Time: 710 ns Started: 630 ns  Scope: top.ap_measure_rise_to_fall File: time_between.sv Line: 33 Expr: $realtime()-current_time<43
#    Local vars : current_time = 630
# error, negedge b=                 870, delta=                  60
# ** Error: Assertion error.
#    Time: 870 ns Started: 810 ns  Scope: top.ap_measure_rise_to_fall File: time_between.sv Line: 33 Expr: $realtime()-current_time<43
#    Local vars : current_time = 810
# ** Error: Assertion error.
#    Time: 950 ns Started: 870 ns  Scope: top.ap_measure_rise_to_fall File: time_between.sv Line: 33 Expr: $realtime()-current_time<43
#    Local vars : current_time = 870

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Ben Cohen
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