The rise and fall/rise of two signals are between 2 time margins

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

Once the signal gets asserted, I capture the current time, then I want to wait until the signal falls and make sure the delta time is between my min and max time. How do you do that comparison when it de-asserts?

property measure_rise_to_fall(bit clk, bit reset, bit sig_a, bit sig_b, time min_time, time max_time);
   time current_time;
   @(posedge clk) disable iff (reset) (($rose(sig_a),current_time=$realtime()) |=> $fell(sig_b) |=> ((min_time > ($realtime()-current_time)) & (max_time < ($realtime() - current_time)))); 

endproperty : measure_rise_to_fall