SystemVerilog array of queues question

SystemVerilog
1

Hope somebody can help me with what on the face of it is very simple.
I’ve been doing SystemVerilog for a total of four days now and my first task is to create an array of queues.

I’ve created with…

int fred [4][$] //4 wide array of queues of int

Now to write to one queue I tried using…

fred[2].push_back(77)

to push the integer 77 into queue 2. Questa does not like the “[2]”.

Thanks.

2

It might help to show a simple complete example and the error you are getting. This works for me.

module top;
   int fred[4][$];
   initial begin
      fred[2].push_back(77);
      $display("fred %p",fred);
   end
endmodule

#fred ‘{’{}, '{}, '{77}, '{}}

3

In reply to dave_59:

Well how embarrassing. I’m a 100% VHDL guy who’s just started with SystemVerilog which may go a little way to explain the error of my ways.

if (push)
    fred[1].push_back(77);
    dick[2].push_back(55);  //line 34
  else if (pop
  ...
  ...

And the error (bearing in mind line 34 was an added line) …

** Error: test.sv(34): near “[”: syntax error, unexpected ‘[’, expecting IDENTIFIER or TYPE_IDENTIFIER

I’ve spent hours banging my head against a wall looking for a ‘technical’ reason but as you can see when I added line 34 I also needed to nest it and the other statements in the branch between ‘begin’ and ‘end’. VHDL doesn’t require them.

Thanks.

4

In reply to Witty:

VHDL to SV transition does take time & pain. A good editor like Emacs/GVim with proper mode setting would help in these kind of cases wherein this would show up with “improper indentation”. Not bullet proof, but could have saved you those few hours (and avoid those “bangs” :-) ).

BTW - this is perhaps why some of our VHDL customers prefer using advanced VHDL testbenches along with PSL for assertions. Random & Coverage can still be achieved via packages such as the one @ www.osvvm.org

Enjoy your SV journey.

Regards
Ajeetha, CVC

5

In reply to ajeetha:

Did you define “dick”?

6

In reply to Enzo Chi:

I was forced to use VHDL and I think VHDL is a good language. But I can’t deny that a lot of good features in SV and UVM can’t be found or easily be done with VHDL. From my opinion, there’s no harm to learn new things.

7

In reply to shrads13:

Re-opening a thread that is over 4 years old can create confusion. Additionally, stating that you have the same error as a previous comment isn’t very descriptive.

You need to post your code that is generating an error along with the exact error message seen. Posting code that can be immediately compiled will make it significantly easier for those trying to help.