In reply to Witty:
VHDL to SV transition does take time & pain. A good editor like Emacs/GVim with proper mode setting would help in these kind of cases wherein this would show up with “improper indentation”. Not bullet proof, but could have saved you those few hours (and avoid those “bangs” :-) ).
BTW - this is perhaps why some of our VHDL customers prefer using advanced VHDL testbenches along with PSL for assertions. Random & Coverage can still be achieved via packages such as the one @ www.osvvm.org
Enjoy your SV journey.
Regards
Ajeetha, CVC