SystemVerilog array of queues question

SystemVerilog
3

In reply to dave_59:

Well how embarrassing. I’m a 100% VHDL guy who’s just started with SystemVerilog which may go a little way to explain the error of my ways.

if (push)
    fred[1].push_back(77);
    dick[2].push_back(55);  //line 34
  else if (pop
  ...
  ...

And the error (bearing in mind line 34 was an added line) …

** Error: test.sv(34): near “[”: syntax error, unexpected ‘[’, expecting IDENTIFIER or TYPE_IDENTIFIER

I’ve spent hours banging my head against a wall looking for a ‘technical’ reason but as you can see when I added line 34 I also needed to nest it and the other statements in the branch between ‘begin’ and ‘end’. VHDL doesn’t require them.

Thanks.