In reply to Enzo Chi:
I was forced to use VHDL and I think VHDL is a good language. But I can’t deny that a lot of good features in SV and UVM can’t be found or easily be done with VHDL. From my opinion, there’s no harm to learn new things.
In reply to Enzo Chi:
I was forced to use VHDL and I think VHDL is a good language. But I can’t deny that a lot of good features in SV and UVM can’t be found or easily be done with VHDL. From my opinion, there’s no harm to learn new things.