System Verilog Program Block

SystemVerilog
1

Hi,

I was trying to write a simple program block in SV.
in my program block, I have tasks, which I declared as externs.

This declaration throws error.

Is extern declaration not allowed in program block?

please help.

Thanks for your support.

Kind Regards

2

In reply to vardhana:

You should never use program blocks. Use a module instead.

3

In reply to cgales:

Why Should i not use?

4

In reply to vardhana:

I read the article, thanks for pointing that.

But, if i use Program then cant i declare the externs?

5

In reply to vardhana:

Extern declarations are associated with classes, not program blocks.

Use a module and completely define all tasks within the module.

6

In reply to vardhana:

Programm blocks are meant to be use to keep the TB executing monitoring tasks in the reactive region preventing race condition between module TB and module DUT.

This can be achieved by using clocking blocks in the interface. Generally speaking the program blocks have more restrictions compared with the module like: modules cannot be declared and extern tasks as well. Since nothing prevents you from calling tasks or so from a module into a program just by passing it as reference from program I believe. So i would recommend you to avoid using program block unless really needed (even if i cannot see use cases, tools not supporting clocking blocks?). Regards

7

In reply to cgales:

Thanks a lot for your inputs

8

In reply to Rsignori92:

Thanks a lot