System verilog fifo

SystemVerilog
, ,
1

Hi,

I am new to system verilog and trying fifo example.
I am not able to get the fifo output ,can you suggest me a solution.
And one more doubt,as it is synchronous we will be getting the output after 1 cycle delay irrespective of keeping the write or read enable high but with respect to my case ,i am not able to get the required output.

Here is my code,
…DESIGN FILE…

module fifo_sample(i_clk,i_rst,read,write,data_in,data_out);
  input logic i_clk,i_rst;
  input logic read,write;
  input logic [3:0] data_in;
  output logic [3:0] data_out;
  reg [3:0]data_out;
  reg [3:0] mem_space[3:0]; //4 * 4 bit array
  reg [3:0] fifo_count;
  
  ////assigning fifo_full and empty condition
  assign fifo_empty=(fifo_count==0);
  assign fifo_full=(fifo_count==7);
  
 
  
  
  //////////////fifo count condition//////////
  always@(posedge i_clk)
   begin
     if((!fifo_full && write) && (!fifo_empty && read))
        fifo_count<=fifo_count+1;
    
   else if(!fifo_full && write && !read)
        fifo_count<=fifo_count+1;
    
    else if(!fifo_full && !write && read)
        fifo_count<=fifo_count-1;
    
    else fifo_count<=fifo_count;
   end
  
  
  ///fifo dat_place in memory/////
  
  always@(posedge i_clk or posedge i_rst)
    begin
      if(i_rst)
        data_out<=0;
      
      else if( write && !read)
        mem_space[fifo_count]<=data_in;
      
      else if(read && !write)
       data_out<=data_in;
      else
        data_out<=0;
      
    end
  /*
  always@(posedge i_clk)
    begin
      if(read)
        data_out<=mem_space[fifo_count];
      else
        data_out<=data_out;
    end
  */
endmodule




....................TESTBENCH...........................

module tb_fifo_sample();
   logic i_clk,i_rst;
   logic read,write;
   logic [3:0] data_in;
   logic [3:0] data_out;
  // reg [3:0]data_out;
   logic [3:0] mem_space[3:0]; //4 * 4 bit array
  logic [3:0] fifo_count;
  
  fifo_sample dut(.*);
  
  initial
    i_clk=0;
  always #5 i_clk=~i_clk;
  
  initial
    begin
      
      $monitor("data_in=%0d,data_out=%0d",data_in,data_out);
      i_rst=1;
      #15;
      i_rst=0;
      #5;
      write=1;
      read=1;
      data_in=4'd1;
       read=1;
      #10;
      data_in=4'd2;
       read=1;
      #10;
      data_in=4'd3;
       read=1;
      
      #10;
      read=1;
      
      #300 $finish();
      
    end
  
  initial
    begin
      $dumpfile("dump.vcd");
      $dumpvars(1);
    end
endmodule
2

In reply to veeresh_03:
Please use code tags to make your code more readable, IO have added them for you this time. It would also help if you provided information about the results you are seeing versus what you expect to see.

One of your problems is you do not reset fifo_count.

3

In reply to veeresh_03:
Your approach to the FIFO is incorrect. A typical FIFO has 2 pointers: A WRITE pointer and a READ pointer. You only have ONE pointer, and that would not work.
On WRITEs, you use the mem_space (mem_space[fifo_count]<=data_in;). On READs you just transfer the input data to the output (else if(read && !write) data_out<=data_in;). ?? That is not a FIFO.
In my SVA Handbook 4th Edition I use a FIFO to demonstrate the definition of requirements for a FIFO, and a set of assertions for a FIFO.
Am giving you links to my model. Try to understand it. Also, use assertions.
BTW, don’t use the “reg”, use “logic”.
HTTP://SystemVerilog.US/VF/fifo_rtl.sv
HTTP://SystemVerilog.US/VF/fifo_props.sv
HTTP://SystemVerilog.US/VF/fifo_if.sv

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

  1. SVA Alternative for Complex Assertions
    Verification Horizons - March 2018 Issue | Verification Academy
  2. SVA: Package for dynamic and range delays and repeats | Verification Academy
  3. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
4

In reply to dave_59:

hi dave,

I am expecting,

///////this is my stimulus/////////
rst=0
write =1;

for(int i=0;i<5;i++)
begin
data_in=i+1;
end

read=1

////////expecting this out put////
data_in=1,data_out=1
data_in=2,data_out=2
data_in=3,data_out=3
data_in=4,data_out=4

PS:I am trying to upload the waveform but i am not able to do so,Sorry for the inconvinience.

Thanks & Regards,
Veeresh

5

In reply to ben@SystemVerilog.us:

hi ben,

[*] yes i understood that part,but when i changed it to two pointers like this.
mem_space[fifo_count]<=data_in;

data_out<=mem_space[fifo_count];

[*] and tried the other way around by using two pointers also,
mem_space[write_ptr]<=data_in;

data_out<=mem_space[read_ptr];

[*] I had set the two different pointers,but but if i havve set the two pointers differently ,how can they point to a common memory from where they can copy the data,
I guess ,i am missing out on some point here.

Thanks & regards,
Veeresh

6

In reply to veeresh_03:
There are IPs with multiple ports. For example:
https://www.intel.com/content/www/us/en/programmable/documentation/eis1413425716965.html
RAM: 2-PORT Simple dual-port RAM
Simultaneous one read and one write operations to different locations.
Supports error correction code (ECC). Supports freeze logic feature.

If the FIFO is small, you can use registers. But I believe that a good sysnthesis tool can help you in that regards. We don’t discuss tool. If you have an specific IP. then ypu’ll have to instantiate the IP and do your design around it.

For a FIFO, you do need 2 pointers.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

  1. SVA Alternative for Complex Assertions
    Verification Horizons - March 2018 Issue | Verification Academy
  2. SVA: Package for dynamic and range delays and repeats | Verification Academy
  3. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy