In reply to veeresh_03:
Your approach to the FIFO is incorrect. A typical FIFO has 2 pointers: A WRITE pointer and a READ pointer. You only have ONE pointer, and that would not work.
On WRITEs, you use the mem_space (mem_space[fifo_count]<=data_in;). On READs you just transfer the input data to the output (else if(read && !write) data_out<=data_in;). ?? That is not a FIFO.
In my SVA Handbook 4th Edition I use a FIFO to demonstrate the definition of requirements for a FIFO, and a set of assertions for a FIFO.
Am giving you links to my model. Try to understand it. Also, use assertions.
BTW, don’t use the “reg”, use “logic”.
HTTP://SystemVerilog.US/VF/fifo_rtl.sv
HTTP://SystemVerilog.US/VF/fifo_props.sv
HTTP://SystemVerilog.US/VF/fifo_if.sv
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA: Package for dynamic and range delays and repeats | Verification Academy
- SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy