In reply to warlocklw:
Try the accept_on
Note that this is the async accept_on that when true yields a vacuous result.
The action block resets the “cancel” bit to 0 on a pass or fail.
You don’t need the |-> or the l_source, l_target.
You may need the “timeunit 1ns; timeprecision 100ps;” // set values as needed
Your assertion checks that th 2 signals are in sync.
module tb;
bit source, target, cancel;
realtime calibration_value=0.1;
function void set_cancel(realtime src, trgt);
if(src>trgt) cancel=1;
else cancel=0;
endfunction
//disable assertion when source > target?
property p1;
//int l_source;
//int l_target;
realtime source_t;
realtime target_t;
@(posedge source) accept_on(cancel)
(1, source_t=$realtime, $display("**** Start **** \nsource_t=%0t",source_t)) ##0
@(posedge target) (1, target_t=$realtime, $display("target_t=%0t",target_t)) ##0
(1, set_cancel(source_t, target_t)) ##0
//(1, l_source=int'(source_t)) |->
// (1, l_target=int'(target_t)) |->
(source_t -target_t) == calibration_value;
endproperty
assert property (p1) begin
set_cancel(1.0, 1.0); // reset cancel on pass
$display("----- End -----");
end
else
begin
set_cancel(1.0, 1.0); // reset on fail
$display("----- End -----");
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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