SVA to check clock toggling for a fixed number of cycles

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

sclk must be stable and toggling before ACK asserts (min 4 SCLKs)
 sclk must be stable and toggling after ACK de-asserts (min 8 SCLKs)
 sclk must be stable and toggling when both the REQ and ACK are asserted

Here you go, this is what I need to do.

Thanks