SVA $stable getting set at first cycle of the simulation

SystemVerilog
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1

$stable is getting set at the very first clock event in the simulation even though the signal is stable .This is creating an unwanted attempt when I am trying to capture the actual changes in the data. I checked it with the following assertion


 	a_check_stable:assert property (@(posedge clk)
         $stable(d)) ;

which is the best method to resolve this issue?

2

In reply to vishnu_intel:

The general coding guideline in SVA is to use ##N delay when using $rose/$fell/$stable/$past etc. In your example do:


a_check_stable:assert property (@(posedge clk)
        ##1 $stable(d)) ;

Are you checking for a stuck-at-1/0 value on d here?

Regards
Srini
www.verifworks.com

3

In reply to Srini @ CVCblr.com:

I am trying to check whether a signal is asserted for minimum 3 clock edges for a synchronizer. I used something like this


property d_stable;
@(posedge clk) disable iff(!clr_b )
!($stable(d))  |=> $stable(d) [*2];
endproperty : d_stable

The above code shows false attempt at the beginning of the simulation.

Then I tried this code, which I think is working


property d_stable;
@(posedge clk) disable iff(!clr_b )
!($stable(d) || $isunknown($past(d)))  |=> $stable(d) [*2];
endproperty : d_stable
4

In reply to vishnu_intel:

Though your second solution would do the job, the recommended coding style is to use ##N in the antecedent.


property d_stable_better;
@(posedge clk) disable iff(!clr_b )
##3 !($stable(d))  |=> $stable(d) [*2];
endproperty : d_stable_better

Rationale - with $stable/$past etc. you infer a memory/FF. As a good designer you want to take care of initial values and in this case you are delaying the checking by 3 clocks as per the user scenario. Also some formal tools require this style to formally verify assertions.

Good Luck
Srini
www.verifworks.com