SVA $stable getting set at first cycle of the simulation

In reply to vishnu_intel:

The general coding guideline in SVA is to use ##N delay when using $rose/$fell/$stable/$past etc. In your example do:


a_check_stable:assert property (@(posedge clk)
        ##1 $stable(d)) ;

Are you checking for a stuck-at-1/0 value on d here?

Regards
Srini
www.verifworks.com

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