SVA $stable getting set at first cycle of the simulation

SystemVerilog
, , ,
3

In reply to Srini @ CVCblr.com:

I am trying to check whether a signal is asserted for minimum 3 clock edges for a synchronizer. I used something like this


property d_stable;
@(posedge clk) disable iff(!clr_b )
!($stable(d))  |=> $stable(d) [*2];
endproperty : d_stable

The above code shows false attempt at the beginning of the simulation.

Then I tried this code, which I think is working


property d_stable;
@(posedge clk) disable iff(!clr_b )
!($stable(d) || $isunknown($past(d)))  |=> $stable(d) [*2];
endproperty : d_stable