SVA Sequence Subtleties (Sequence fusion / Sequence concatenation)

SystemVerilog
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3

In reply to ben@SystemVerilog.us:
You sequence declaration does not look correct. You need to explain your requirements.
This is my guess at what you need


sequence response_queue(sig); 
 int num_ahead;
 @(posedge clk) ($rose(sig), num_ahead=data) ##0 
  (num_ahead > 0 && transaction_advance, num_ahead--)[*1:$] ##1
   num_ahead <= 0);
endsequence

(num_ahead == 0) [->1] cause way too many threads.
I strongly urge you to read my papers