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I have a expression in my property antecedent, However property is becoming active even though one of the field in expression is not as per the condition.
I followed one of the post and changed “&&” to “##0” in my expression, However my property is becoming active event one signal is not as per the expectation in antecedent.
I need help with SVA coding here.
Thank you for the helping on the SVA.
In reply to Verif_Learner_SG:
Show your code and tests. You can use edaplayground.
What you are expressing is difficult to understand. Also, I see no antecedent.
The following 2 papers written by me make the point the for a property to be true, SVA requires that each of the threads of that antecedent with a range delay or a range repeat statement must be exercised with its appropriate consequent.
1 Understanding the SVA Engine Using the Fork-Join Model
Using a model, the paper addresses important concepts about attempts and threads. Emphasizes the total independence of attempts.
2 Reflections on Users’ Experiences with SVA, part 1
Important concepts on EXPRESSING REQUIREMENTS,
Terminology, threads in ranges and repeats in antecedents, multiple antecedents.
This response addresses the quick implementation of a TB. It might be of interest to you.
Getting started with verification with SystemVerilog
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.
