SVA difference between 2 properties

SystemVerilog
3

In reply to ben@SystemVerilog.us:

Thanks Ben.
I think I am still not sure why the property

XYZ: assert property ( @(posedge clk) en |-> (a [->1]) within (b [->1]));

failed at 45ns.

Based on your comments and the message from the simulator, I guess the evaluation started at 45ns, and at 45ns, en is true, b is true but a is not, so the assertion failed. If that is case, does it mean below are same ?

XYZ: assert property ( @(posedge clk) en |-> (a [->1]) within (b [->1]));
    ABC: assert property ( @(posedge clk) en |->  a within (b [->1]));

or maybe the assertion XYZ does not really make sense?

Thanks