Assertions not being covered

SystemVerilog
,
1

Hi,

Why am I not able to see the success message of a few of my transactions though it had been hit/covered as per my knowledge?
Can anyone also please suggest a good coding style of assertions? And also the syntax for assertion coverage (how to determine my coverage % of assertions)?

Link to EDA Playground :APB_SLAVE

Thank You

2

In reply to sai_pra99:

The way you apply your test patterns should not match your clocks.
Thus, you should use the clocking events and nonblocking assignments

 
initial forever #10 p_clk=!p_clk;
// OK, but use the logical not. 
//..... 
// instead of 
      #20;
      p_enable=1;
      #40
      p_rstn=1; 
// Use the clocking event and nonblocking assignments 
      @(posedge p_clk);
      //#20;
      p_enable <=1;
      repeat(2)@(posedge p_clk);
      // #40
      p_rstn <=1;

Make those changes first.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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3

In reply to ben@SystemVerilog.us:

Same comment as above for the RTL design.
When you have an always @(posedge clk) use nonblocking assignments (I. E., the <= instead of the =)

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4

In reply to ben@SystemVerilog.us:

Hi, I have made the necessary changes and I guess it works fine now.
But, I am quite unsure whether all the assertions have fired or not. So to check I am trying to collect coverage.
Could you please instruct me on how to collect coverage?. This is my first time.

LINK to EDA playground: APB_SLAVE

Update: Just got to know that the simulator tool automatically does that without the engineer’s interference unlike get_inst_covergae(). Is that even possible with the EDA playground as I do not have any VPN access or ownership of the industry tool available?

Thank You